PFB Functional Description

The first stage of data processing is a coarse channelization handled by a 4096-channel polyphase filter bank (PFB). A general description of the PFB algorithm and architecture can be found here. The PFB takes a 16-bit (8 bits real, 8 bits imaginary) input from the DDC per cycle which is passed through a 4K-channel, 8-tap FIR filter that allows bit growth from 8 to 18 bits (18.17 signed). The post-FIR data is then fed into a 4096-point biplex pipelined complex FFT with programmable downshifts, which maintains 18.17 signed data at the output.

FIR Filter Notes

The first few weeks of observation with the spectrometer revealed interactions between the PFB FIR filter's rolloff characteristics and the averaging and thresholding operations. The result was a suppression of bins at the PFB edges, causing those bins to always be below threshold and creating gaps in the thresholded spectrum, as shown in Figure 1.

A quick-fix solution to this problem was present in the 20050810 revision of the FPGA gateware, which changed the overlap factor on the PFB FIR filter from 1.0 to 1.2. Figure 2 shows a comparison of the two filter shapes. The change alleviates the attenuation of edge bins, but allows more power leakage between adjacent PFB bins (Figure 3). The increased inter-bin aliasing was deemed acceptable for the exploratory work, but a better long-term solution will be to increase the number of taps in the FIR filter, which should give sharper transition bands and less attenuation due to filter roll-off.