Model { Name "spec_demo_1" Version 6.2 MdlSubVersion 0 GraphicalInterface { NumRootInports 0 NumRootOutports 0 ParameterArgumentNames "" ComputedModelVersion "1.45" NumModelReferences 0 NumTestPointedSignals 0 } SavedCharacterEncoding "ibm-5348_P100-1997" SaveDefaultBlockParams on SampleTimeColors off LibraryLinkDisplay "all" WideLines off ShowLineDimensions off ShowPortDataTypes on ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ShowTestPointIcons on ShowViewerIcons on SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off CovReportOnPause on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off Created "Wed Jun 27 10:24:50 2007" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "chappy" ModifiedDateFormat "%" LastModifiedDate "Thu Jul 05 15:20:28 2007" ModelVersionFormat "1.%" ConfigurationManager "None" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigDurationFloating "auto" ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on StrictBusMsg "None" ProdHWDeviceType "32-bit Generic" ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { Type "Handle" Dimension 1 Simulink.ConfigSet { $ObjectID 1 Version "1.1.0" Array { Type "Handle" Dimension 7 Simulink.SolverCC { $ObjectID 2 Version "1.1.0" StartTime "0.0" StopTime "200" AbsTol "auto" FixedStep "auto" InitialStep "auto" MaxNumMinSteps "-1" MaxOrder 5 ExtrapolationOrder 4 NumberNewtonIterations 1 MaxStep "auto" MinStep "auto" RelTol "1e-3" SolverMode "Auto" Solver "ode45" SolverName "ode45" ZeroCrossControl "UseLocalSettings" AlgebraicLoopSolver "TrustRegion" SolverResetMethod "Fast" PositivePriorityOrder off AutoInsertRateTranBlk off SampleTimeConstraint "Unconstrained" RateTranMode "Deterministic" } Simulink.DataIOCC { $ObjectID 3 Version "1.1.0" Decimation "1" ExternalInput "[t, u]" FinalStateName "xFinal" InitialState "xInitial" LimitDataPoints on MaxDataPoints "1000" LoadExternalInput off LoadInitialState off SaveFinalState off SaveFormat "Array" SaveOutput on SaveState off SignalLogging on SaveTime on StateSaveName "xout" TimeSaveName "tout" OutputSaveName "yout" SignalLoggingName "logsout" OutputOption "RefineOutputTimes" OutputTimes "[]" Refine "1" } Simulink.OptimizationCC { $ObjectID 4 Array { Type "Cell" Dimension 5 Cell "ZeroExternalMemoryAtStartup" Cell "ZeroInternalMemoryAtStartup" Cell "InitFltsAndDblsToZero" Cell "OptimizeModelRefInitCode" Cell "NoFixptDivByZeroProtection" PropName "DisabledProps" } Version "1.1.0" BlockReduction on BooleanDataType on ConditionallyExecuteInputs on InlineParams off InlineInvariantSignals off OptimizeBlockIOStorage on BufferReuse on EnforceIntegerDowncast on ExpressionFolding on FoldNonRolledExpr on LocalBlockOutputs on ParameterPooling on RollThreshold 5 SystemCodeInlineAuto off StateBitsets off DataBitsets off UseTempVars off ZeroExternalMemoryAtStartup on ZeroInternalMemoryAtStartup on InitFltsAndDblsToZero on NoFixptDivByZeroProtection off EfficientFloat2IntCast off OptimizeModelRefInitCode off LifeSpan "inf" BufferReusableBoundary on } Simulink.DebuggingCC { $ObjectID 5 Version "1.1.0" RTPrefix "error" ConsistencyChecking "none" ArrayBoundsChecking "none" SignalInfNanChecking "none" AlgebraicLoopMsg "warning" ArtificialAlgebraicLoopMsg "warning" CheckSSInitialOutputMsg on CheckExecutionContextPreStartOutputMsg off CheckExecutionContextRuntimeOutputMsg off SignalResolutionControl "TryResolveAllWithWarning" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" SolverPrmCheckMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskDSMMsg "warning" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" TasksWithSamePriorityMsg "warning" CheckMatrixSingularityMsg "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterPrecisionLossMsg "warning" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" FcnCallInpInsideContextMsg "Use local settings" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SFcnCompatibilityMsg "none" UniqueDataStoreMsg "none" BusObjectLabelMismatch "warning" RootOutportRequireBusObject "warning" AssertControl "UseLocalSettings" EnableOverflowDetection off ModelReferenceIOMsg "none" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" ModelReferenceCSMismatchMessage "none" ModelReferenceSimTargetVerbose off UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" ModelReferenceExtraNoncontSigs "error" } Simulink.HardwareCC { $ObjectID 6 Version "1.1.0" ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 32 ProdBitPerLong 32 ProdIntDivRoundTo "Undefined" ProdEndianess "Unspecified" ProdWordSize 32 ProdShiftRightIntArith on ProdHWDeviceType "32-bit Generic" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 TargetShiftRightIntArith on TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" TargetUnknown off ProdEqTarget on } Simulink.ModelReferenceCC { $ObjectID 7 Version "1.1.0" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" ModelReferenceNumInstancesAllowed "Multi" ModelReferencePassRootInputsByReference on ModelReferenceMinAlgLoopOccurrences off } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" $ObjectID 8 Array { Type "Cell" Dimension 1 Cell "IncludeHyperlinkInReport" PropName "DisabledProps" } Version "1.1.0" SystemTargetFile "grt.tlc" GenCodeOnly off MakeCommand "make_rtw" TemplateMakefile "grt_default_tmf" GenerateReport off SaveLog off RTWVerbose on RetainRTWFile off ProfileTLC off TLCDebug off TLCCoverage off TLCAssert off ProcessScriptMode "Default" ConfigurationMode "Optimized" ConfigAtBuild off IncludeHyperlinkInReport off LaunchReport off TargetLang "C" Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { $ObjectID 9 Array { Type "Cell" Dimension 9 Cell "IgnoreCustomStorageClasses" Cell "InsertBlockDesc" Cell "SFDataObjDesc" Cell "SimulinkDataObjDesc" Cell "DefineNamingRule" Cell "SignalNamingRule" Cell "ParamNamingRule" Cell "InlinedPrmAccess" Cell "CustomSymbolStr" PropName "DisabledProps" } Version "1.1.0" ForceParamTrailComments off GenerateComments on IgnoreCustomStorageClasses on IncHierarchyInIds off MaxIdLength 31 PreserveName off PreserveNameWithParent off ShowEliminatedStatement off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off IncDataTypeInIds off PrefixModelToSubsysFcnNames on CustomSymbolStr "$R$N$M" MangleLength 1 DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" InsertBlockDesc off SimulinkBlockComments on EnableCustomComments off InlinedPrmAccess "Literals" ReqsInCode off } Simulink.GRTTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 10 Array { Type "Cell" Dimension 12 Cell "IncludeMdlTerminateFcn" Cell "CombineOutputUpdateFcns" Cell "SuppressErrorStatus" Cell "ERTCustomFileBanners" Cell "GenerateSampleERTMain" Cell "MultiInstanceERTCode" Cell "PurelyIntegerCode" Cell "SupportNonFinite" Cell "SupportComplex" Cell "SupportAbsoluteTime" Cell "SupportContinuousTime" Cell "SupportNonInlinedSFcns" PropName "DisabledProps" } Version "1.1.0" TargetFcnLib "ansi_tfl_tmw.mat" TargetLibSuffix "" TargetPreCompLibLocation "" GenFloatMathFcnCalls "ANSI_C" UtilityFuncGeneration "Auto" GenerateFullHeader on GenerateSampleERTMain off IsPILTarget off ModelReferenceCompliant on IncludeMdlTerminateFcn on CombineOutputUpdateFcns off SuppressErrorStatus off IncludeFileDelimiter "Auto" ERTCustomFileBanners off SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging on MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime on SupportNonInlinedSFcns on ExtMode off ExtModeStaticAlloc off ExtModeTesting off ExtModeStaticAllocSize 1000000 ExtModeTransport 0 ExtModeMexFile "ext_comm" RTWCAPISignals off RTWCAPIParams off RTWCAPIStates off GenerateASAP2 off } PropName "Components" } } PropName "Components" } Name "Configuration" SimulationMode "normal" CurrentDlgPage "Solver" } PropName "ConfigurationSets" } Simulink.ConfigSet { $PropName "ActiveConfigurationSet" $ObjectID 1 } BlockDefaults { Orientation "right" ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on } BlockParameterDefaults { Block { BlockType Bias Bias "0" SaturateOnIntegerOverflow on } Block { BlockType Constant Value "1" VectorParams1D on OutDataTypeMode "Inherit from 'Constant value'" OutDataType "sfix(16)" ConRadixGroup "Use specified scaling" OutScaling "2^0" SampleTime "inf" } Block { BlockType DiscretePulseGenerator PulseType "Sample based" TimeSource "Use simulation time" Amplitude "1" Period "2" PulseWidth "1" PhaseDelay "0" SampleTime "1" VectorParams1D on } Block { BlockType Gain Gain "1" Multiplication "Element-wise(K.*u)" ParameterDataTypeMode "Same as input" ParameterDataType "sfix(16)" ParameterScalingMode "Best Precision: Matrix-wise" ParameterScaling "2^0" OutDataTypeMode "Same as input" OutDataType "sfix(16)" OutScaling "2^0" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType Inport UseBusObject off BusObject "BusObject" BusOutputAsStruct off PortDimensions "-1" SampleTime "-1" DataType "auto" OutDataType "sfix(16)" OutScaling "2^0" SignalType "auto" SamplingMode "auto" Interpolate on } Block { BlockType Logic Operator "AND" Inputs "2" AllPortsSameDT on OutDataTypeMode "Logical (see Configuration Parameters: Optimiza" "tion)" LogicDataType "uint(8)" SampleTime "-1" } Block { BlockType Outport Port "1" UseBusObject off BusObject "BusObject" BusOutputAsStruct off PortDimensions "-1" SampleTime "-1" DataType "auto" OutDataType "sfix(16)" OutScaling "2^0" SignalType "auto" SamplingMode "auto" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType RelationalOperator Operator ">=" InputSameDT on LogicOutDataTypeMode "Logical (see Configuration Parameters: Optimiza" "tion)" LogicDataType "uint(8)" ZeroCross on SampleTime "-1" } Block { BlockType Scope Floating off ModelBased off TickLabels "OneTimeTick" ZoomMode "on" Grid "on" TimeRange "auto" YMin "-5" YMax "5" SaveToWorkspace off SaveName "ScopeData" LimitDataPoints on MaxDataPoints "5000" Decimation "1" SampleInput off SampleTime "0" } Block { BlockType "S-Function" FunctionName "system" SFunctionModules "''" PortCounts "[]" } Block { BlockType Sin SineType "Time based" TimeSource "Use simulation time" Amplitude "1" Bias "0" Frequency "1" Phase "0" Samples "10" Offset "0" SampleTime "-1" VectorParams1D on } Block { BlockType SubSystem ShowPortLabels on Permissions "ReadWrite" PermitHierarchicalResolution "All" SystemSampleTime "-1" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" SimViewingDevice off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" } Block { BlockType Terminator } } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } System { Name "spec_demo_1" Location [552, 100, 1421, 643] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" ReportName "simulink-default.rpt" Block { BlockType Reference Name " System Generator" Tag "genX" Ports [] Position [22, 13, 73, 63] ShowName off AttributesFormatString "System\\nGenerator" UserDataPersistent on UserData "DataTag0" SourceBlock "xbsIndex_r3/ System Generator" SourceType "Xilinx System Generator" ShowPortLabels on xilinxfamily "Virtex2P" part "xc2vp50" speed "-7" package "ff1152" synthesis_tool "XST" directory "./spec_demo_1/sysgen" testbench off simulink_period "1" sysclk_period "8" incr_netlist off trim_vbits "Everywhere in SubSystem" dbl_ovrd "According to Block Masks" core_generation "According to Block Masks" run_coregen off deprecated_control off eval_field "0" } Block { BlockType Reference Name "Constant" Ports [0, 1] Position [270, 275, 315, 305] SourceBlock "xbsIndex_r3/Constant" SourceType "Xilinx Constant Block" const "-1" equ "P=C" arith_type "Signed (2's comp)" n_bits "6" bin_pt "0" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" iostate "0" explicit_period on period "1" dbl_ovrd off } Block { BlockType Reference Name "Constant1" Ports [0, 1] Position [620, 35, 665, 65] SourceBlock "xbsIndex_r3/Constant" SourceType "Xilinx Constant Block" const "1" equ "P=C" arith_type "Boolean" n_bits "6" bin_pt "0" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" iostate "0" explicit_period on period "1" dbl_ovrd off } Block { BlockType Reference Name "Constant2" Ports [0, 1] Position [105, 230, 150, 260] SourceBlock "xbsIndex_r3/Constant" SourceType "Xilinx Constant Block" const "0" equ "P=C" arith_type "Unsigned" n_bits "27" bin_pt "0" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" iostate "0" explicit_period on period "1" dbl_ovrd off } Block { BlockType Constant Name "Constant4" Position [30, 460, 60, 490] Value "0" } Block { BlockType Constant Name "Constant5" Position [25, 525, 55, 555] Value "0" } Block { BlockType Reference Name "Convert" Ports [1, 1] Position [345, 306, 380, 324] SourceBlock "xbsIndex_r3/Convert" SourceType "Xilinx Converter Block" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" quantization "Truncate" overflow "Wrap" latency "0" explicit_period off period "1" dbl_ovrd off show_param off inserted_by_tool off pipeline off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Convert1" Ports [1, 1] Position [345, 326, 380, 344] SourceBlock "xbsIndex_r3/Convert" SourceType "Xilinx Converter Block" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" quantization "Truncate" overflow "Wrap" latency "0" explicit_period off period "1" dbl_ovrd off show_param off inserted_by_tool off pipeline off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Convert2" Ports [1, 1] Position [375, 346, 410, 364] SourceBlock "xbsIndex_r3/Convert" SourceType "Xilinx Converter Block" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" quantization "Truncate" overflow "Wrap" latency "0" explicit_period off period "1" dbl_ovrd off show_param off inserted_by_tool off pipeline off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Convert3" Ports [1, 1] Position [335, 366, 370, 384] SourceBlock "xbsIndex_r3/Convert" SourceType "Xilinx Converter Block" arith_type "Signed (2's comp)" n_bits "12" bin_pt "11" quantization "Truncate" overflow "Wrap" latency "0" explicit_period off period "1" dbl_ovrd off show_param off inserted_by_tool off pipeline off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Counter" Ports [0, 1] Position [105, 150, 155, 200] SourceBlock "xbsIndex_r3/Counter" SourceType "Xilinx Counter Block" cnt_type "Free Running" n_bits "41" bin_pt "0" arith_type "Unsigned" start_count "0" cnt_to "Inf" cnt_by_val "1" operation "Up" explicit_period off period "1" load_pin off rst off en off dbl_ovrd off show_param off use_rpm on gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay" Ports [1, 1] Position [865, 33, 895, 57] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "6" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay1" Ports [1, 1] Position [865, 58, 895, 82] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "6" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay2" Ports [1, 1] Position [870, 263, 900, 287] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "6" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Gateway Out" Ports [1, 1] Position [1175, 119, 1230, 141] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Gateway Out1" Ports [1, 1] Position [1175, 164, 1230, 186] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Gateway Out2" Ports [1, 1] Position [1175, 209, 1230, 231] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Gateway Out3" Ports [1, 1] Position [1160, 469, 1215, 491] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Gateway Out4" Ports [1, 1] Position [1160, 514, 1215, 536] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Gateway Out5" Ports [1, 1] Position [1160, 559, 1215, 581] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Gateway Out6" Ports [1, 1] Position [1160, 309, 1215, 331] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Gateway Out7" Ports [1, 1] Position [1175, 254, 1230, 276] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Gateway Out8" Ports [1, 1] Position [1160, 399, 1215, 421] SourceBlock "xbsIndex_r3/Gateway Out" SourceType "Xilinx Gateway Out" output_type "Double" nbits "8" bin_pt "6" arith_type "Boolean" quantization "Truncate" overflow "Wrap" hdl_port on timing_constraint "None" locs_specified off LOCs "{}" needs_fixed_name off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Relational" Ports [2, 1] Position [205, 178, 250, 222] SourceBlock "xbsIndex_r3/Relational" SourceType "Xilinx Relational Block" mode "a=b" latency "1" explicit_period off period "1" en off dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Scope Name "Scope" Ports [4] Position [1255, 109, 1280, 286] Location [6, 49, 1022, 733] Open off NumInputPorts "4" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" } YMin "-5~-5~-5~-5" YMax "5~5~5~5" DataFormat "StructureWithTime" LimitDataPoints off } Block { BlockType Scope Name "Scope1" Ports [3] Position [1240, 455, 1265, 595] Location [1, 45, 1019, 382] Open off NumInputPorts "3" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" } YMin "-5~-5~-5" YMax "5~5~5" SaveName "ScopeData1" DataFormat "StructureWithTime" LimitDataPoints off } Block { BlockType Scope Name "Scope2" Ports [2] Position [1240, 290, 1265, 430] Location [6, 49, 1024, 386] Open off NumInputPorts "2" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" } YMin "-5~-5" YMax "5~5" SaveName "ScopeData2" DataFormat "StructureWithTime" LimitDataPoints off } Block { BlockType Reference Name "Shared BRAM" Tag "xps:bram" Ports [3, 1] Position [1050, 291, 1130, 349] BackgroundColor "[1.000000, 1.000000, 0.000000]" SourceBlock "xps_library/Shared BRAM" SourceType "" ShowPortLabels on arith_type "Signed (2's comp)" addr_width "11" data_width "32" data_bin_pt "22" init_vals "[1:2^11]" sample_rate "1" } Block { BlockType Reference Name "Shared BRAM1" Tag "xps:bram" Ports [3, 1] Position [1050, 381, 1130, 439] BackgroundColor "[1.000000, 1.000000, 0.000000]" SourceBlock "xps_library/Shared BRAM" SourceType "" ShowPortLabels on arith_type "Signed (2's comp)" addr_width "11" data_width "32" data_bin_pt "22" init_vals "[1:2^11]" sample_rate "1" } Block { BlockType Sin Name "Sine Wave" Ports [0, 1] Position [25, 330, 55, 360] SineType "Sample based" Samples "4" SampleTime "1" } Block { BlockType Reference Name "XSG core config" Tag "xps:xsg" Ports [] Position [105, 14, 151, 57] BackgroundColor "[1.000000, 1.000000, 0.000000]" SourceBlock "xps_library/XSG core config" SourceType "xsg core config" ShowPortLabels on hw_sys "iBOB" ibob_linux off clk_src "sys_clk" gpio_clk_io_group "iBOB:sma" gpio_clk_bit_index "0" clk_rate "125" sample_period "1" synthesis_tool "XST" mpc_type "powerpc405" } Block { BlockType Reference Name "adc" Tag "xps:adc" Ports [4, 17] Position [90, 309, 235, 571] BackgroundColor "[1.000000, 1.000000, 0.000000]" SourceBlock "xps_library/adc" SourceType "adc" ShowPortLabels on adc_brd "iBOB:adc0" adc_clk_rate "500" adc_interleave off sample_period "1" } Block { BlockType SubSystem Name "fft_wideband_real" Ports [6, 3] Position [470, 269, 610, 381] BackgroundColor "[0.501961, 1.000000, 0.501961]" AttributesFormatString "FFTSize=6, n_inputs=2" AncestorBlock "casper_library/FFTs/fft_wideband_real" UserDataPersistent on UserData "DataTag1" TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" MaskType "fft_wideband_real" MaskPromptString "Size of FFT: (2^?)|Bit Width|Number of Simultan" "eous Inputs: (2^?)|Quantization Behavior|Overflow Behavior|Add Latency|Mult L" "atency|BRAM Latency" MaskStyleString "edit,edit,edit,popup(Truncate|Round (unbiased:" " +/- Inf)|Round (unbiased: Even Values)),popup(Wrap|Saturate|Error),edit,edi" "t,edit" MaskTunableValueString "on,on,on,on,on,on,on,on" MaskCallbackString "|||||||" MaskEnableString "on,on,on,on,on,on,on,on" MaskVisibilityString "on,on,on,on,on,on,on,on" MaskToolTipString "on,on,on,on,on,on,on,on" MaskVarAliasString ",,,,,,," MaskVariables "FFTSize=@1;BitWidth=@2;n_inputs=@3;quantization" "=&4;overflow=&5;add_latency=@6;mult_latency=@7;bram_latency=@8;" MaskInitialization "fft_wideband_real_init(gcb,...\n 'FFTSize', " "FFTSize,...\n 'BitWidth', BitWidth,...\n 'n_inputs', n_inputs,...\n " "'quantization', quantization,...\n 'overflow', overflow,...\n 'add_late" "ncy', add_latency,...\n 'mult_latency', mult_latency,...\n 'bram_latenc" "y', bram_latency);" MaskSelfModifiable on MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskIconUnits "autoscale" MaskValueString "6|12|2|Truncate|Wrap|2|3|2" MaskTabNameString ",,,,,,," System { Name "fft_wideband_real" Location [62, 128, 911, 677] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "sync" Position [30, 17, 60, 33] NamePlacement "alternate" Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "shift" Position [30, 47, 60, 63] Port "2" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "in0" Position [30, 102, 60, 118] Port "3" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "in1" Position [30, 202, 60, 218] Port "4" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "in2" Position [30, 302, 60, 318] Port "5" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "in3" Position [30, 402, 60, 418] Port "6" IconDisplay "Port number" LatchInput off } Block { BlockType SubSystem Name "fft_biplex_real_4x0" Ports [6, 6] Position [100, 100, 220, 220] BackgroundColor "[0.501961, 0.501961, 0.501961]" AttributesFormatString "FFTSize=4, BitWidth=12" AncestorBlock "casper_library/FFTs/fft_biplex_real_4x" UserDataPersistent on UserData "DataTag2" TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" MaskType "fft_biplex_real_4x" MaskPromptString "Size of FFT: (2^? pnts)|Bitwidth: (Max Effi" "ciency at 18 bits)|Quantization Behavior|Overflow Behavior|Add Latency|Mult L" "atency|BRAM Latency" MaskStyleString "edit,edit,popup(Truncate|Round (unbiased: " "+/- Inf)|Round (unbiased: Even Values)),popup(Wrap|Saturate|Error),edit,edit" ",edit" MaskTunableValueString "on,on,on,on,on,on,on" MaskCallbackString "||||||" MaskEnableString "on,on,on,on,on,on,on" MaskVisibilityString "on,on,on,on,on,on,on" MaskToolTipString "on,on,on,on,on,on,on" MaskVarAliasString ",,,,,," MaskVariables "FFTSize=@1;BitWidth=@2;quantization=&3;over" "flow=&4;add_latency=@5;mult_latency=@6;bram_latency=@7;" MaskInitialization "fft_biplex_real_4x_init(gcb,...\n 'FFTSi" "ze', FFTSize,...\n 'BitWidth', BitWidth,...\n 'quantization', quantizat" "ion,...\n 'overflow', overflow,...\n 'add_latency', add_latency,...\n " " 'mult_latency', mult_latency,...\n 'bram_latency', bram_latency);\n\n" MaskSelfModifiable on MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskIconUnits "autoscale" MaskValueString "4|12|Truncate|Wrap|2|3|2" MaskTabNameString ",,,,,," System { Name "fft_biplex_real_4x0" Location [59, 184, 901, 488] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "pol1" Position [15, 33, 45, 47] Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "pol2" Position [15, 63, 45, 77] Port "2" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "pol3" Position [15, 93, 45, 107] Port "3" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "pol4" Position [15, 123, 45, 137] Port "4" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "sync" Position [15, 153, 45, 167] Port "5" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "shift" Position [15, 178, 45, 192] Port "6" IconDisplay "Port number" LatchInput off } Block { BlockType SubSystem Name "bi_real_unscr_4x" Ports [3, 5] Position [350, 102, 435, 188] TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" MaskPromptString "Size of FFT (2^?):|BRAM Latency" MaskStyleString "edit,edit" MaskTunableValueString "on,on" MaskCallbackString "|" MaskEnableString "on,on" MaskVisibilityString "on,on" MaskToolTipString "on,on" MaskVarAliasString "," MaskVariables "FFTSize=@1;bram_latency=@2;" MaskInitialization "blk = gcb;\n\nset_param([blk,'/reorder'" "],'map', mat2str(bit_reverse(0:2^(FFTSize-1)-1, FFTSize-1)));\nset_param([blk" ",'/reorder'],'bram_latency', num2str(bram_latency));\nset_param([blk,'/reorde" "r1'],'map', mat2str(bit_reverse(2^(FFTSize-1)-1:-1:0, FFTSize-1)));\nset_para" "m([blk,'/reorder1'],'bram_latency', num2str(bram_latency));\nset_param([blk,'" "/reorder2'],'map', mat2str(2^(FFTSize-1)-1:-1:0));\nset_param([blk,'/reorder2" "'],'bram_latency', num2str(bram_latency));" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskIconUnits "autoscale" MaskValueString "4|2" MaskTabNameString "," System { Name "bi_real_unscr_4x" Location [2, 74, 1014, 724] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "even" Position [35, 133, 65, 147] Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "odd" Position [50, 218, 80, 232] Port "2" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "sync" Position [35, 93, 65, 107] Port "3" IconDisplay "Port number" LatchInput off } Block { BlockType Reference Name "Constant" Ports [0, 1] Position [25, 195, 65, 215] SourceBlock "xbsIndex_r3/Constant" SourceType "Xilinx Constant Block" const "1" equ "P=C" arith_type "Boolean" n_bits "1" bin_pt "0" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" iostate "0" explicit_period on period "1" dbl_ovrd off } Block { BlockType Reference Name "Constant1" Ports [0, 1] Position [225, 51, 260, 69] SourceBlock "xbsIndex_r3/Constant" SourceType "Xilinx Constant Block" const "2^(FFTSize-1)" equ "P=C" arith_type "Unsigned" n_bits "FFTSize" bin_pt "0" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" iostate "0" explicit_period on period "1" dbl_ovrd off } Block { BlockType Reference Name "Constant2" Ports [0, 1] Position [225, 176, 260, 194] SourceBlock "xbsIndex_r3/Constant" SourceType "Xilinx Constant Block" const "0" equ "P=C" arith_type "Unsigned" n_bits "FFTSize" bin_pt "0" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" iostate "0" explicit_period on period "1" dbl_ovrd off } Block { BlockType Reference Name "Constant5" Ports [0, 1] Position [535, 325, 575, 345] SourceBlock "xbsIndex_r3/Constant" SourceType "Xilinx Constant Block" const "1" equ "P=C" arith_type "Boolean" n_bits "1" bin_pt "0" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" iostate "0" explicit_period on period "1" dbl_ovrd off } Block { BlockType Reference Name "Counter" Ports [1, 1] Position [225, 82, 260, 118] SourceBlock "xbsIndex_r3/Counter" SourceType "Xilinx Counter Block" cnt_type "Free Running" n_bits "FFTSize" bin_pt "0" arith_type "Unsigned" start_count "0" cnt_to "Inf" cnt_by_val "1" operation "Up" explicit_period off period "1" load_pin off rst on en off dbl_ovrd off show_param off use_rpm on gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay" Ports [1, 1] Position [265, 209, 295, 241] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Mux" Ports [3, 1] Position [365, 192, 390, 258] SourceBlock "xbsIndex_r3/Mux" SourceType "Xilinx Multiplexer Block" inputs "2" precision "Full" arith_type "Signed (2's comp)" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "1" explicit_period off period "1" en off dbl_ovrd off show_param off mux_type off use_rpm off gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Mux1" Ports [3, 1] Position [365, 107, 390, 173] SourceBlock "xbsIndex_r3/Mux" SourceType "Xilinx Multiplexer Block" inputs "2" precision "Full" arith_type "Signed (2's comp)" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "1" explicit_period off period "1" en off dbl_ovrd off show_param off mux_type off use_rpm off gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Mux2" Ports [3, 1] Position [365, 402, 390, 468] SourceBlock "xbsIndex_r3/Mux" SourceType "Xilinx Multiplexer Block" inputs "2" precision "Full" arith_type "Signed (2's comp)" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "1" explicit_period off period "1" en off dbl_ovrd off show_param off mux_type off use_rpm off gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Mux3" Ports [3, 1] Position [365, 317, 390, 383] SourceBlock "xbsIndex_r3/Mux" SourceType "Xilinx Multiplexer Block" inputs "2" precision "Full" arith_type "Signed (2's comp)" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "1" explicit_period off period "1" en off dbl_ovrd off show_param off mux_type off use_rpm off gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Relational" Ports [2, 1] Position [285, 153, 330, 197] SourceBlock "xbsIndex_r3/Relational" SourceType "Xilinx Relational Block" mode "a=b" latency "0" explicit_period off period "1" en off dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Relational1" Ports [2, 1] Position [285, 68, 330, 112] SourceBlock "xbsIndex_r3/Relational" SourceType "Xilinx Relational Block" mode "a=b" latency "0" explicit_period off period "1" en off dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "complex_addsub" Ports [2, 2] Position [410, 200, 495, 235] SourceBlock "casper_library/Misc/complex_addsub" SourceType "" ShowPortLabels on BitWidth "BitWidth" add_latency "add_latency" } Block { BlockType Reference Name "complex_addsub1" Ports [2, 2] Position [410, 410, 495, 445] SourceBlock "casper_library/Misc/complex_addsub" SourceType "" ShowPortLabels on BitWidth "BitWidth" add_latency "add_latency" } Block { BlockType SubSystem Name "delay0" Ports [1, 1] Position [525, 195, 570, 225] BackgroundColor "[0.501961, 1.000000, 0.501961]" AttributesFormatString "%" LinkData { BlockName "delay_bram" DialogParameters { DelayLen "2^(FFTSize-1)" bram_latency "bram_latency" } BlockName "delay_slr" DialogParameters { DelayLen "2^(FFTSize-1)" } } BlockChoice "delay_slr" TemplateBlock "casper_library/Delays/delay" MemberBlocks "delay_bram,delay_slr" TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" System { Name "delay0" Location [148, 182, 646, 482] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "In1" Position [20, 40, 40, 60] Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Reference Name "delay_slr" Ports [1, 1] Position [100, 40, 140, 80] BackgroundColor "[0.501961, 1.000000, 0.501961]" SourceBlock "casper_library/Delays/delay_slr" SourceType "delay_slr" ShowPortLabels on DelayLen "2^(FFTSize-1)" } Block { BlockType Outport Name "Out1" Position [200, 40, 220, 60] IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "In1" SrcPort 1 DstBlock "delay_slr" DstPort 1 } Line { SrcBlock "delay_slr" SrcPort 1 DstBlock "Out1" DstPort 1 } } } Block { BlockType SubSystem Name "delay1" Ports [1, 1] Position [525, 250, 570, 280] BackgroundColor "[0.501961, 1.000000, 0.501961]" AttributesFormatString "%" LinkData { BlockName "delay_bram" DialogParameters { bram_latency "bram_latency" DelayLen "2^(FFTSize-1)" } BlockName "delay_slr" DialogParameters { DelayLen "2^(FFTSize-1)" } } BlockChoice "delay_slr" TemplateBlock "casper_library/Delays/delay" MemberBlocks "delay_bram,delay_slr" TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" System { Name "delay1" Location [148, 182, 646, 482] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "In1" Position [20, 40, 40, 60] Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Reference Name "delay_slr" Ports [1, 1] Position [100, 40, 140, 80] BackgroundColor "[0.501961, 1.000000, 0.501961]" SourceBlock "casper_library/Delays/delay_slr" SourceType "delay_slr" ShowPortLabels on DelayLen "2^(FFTSize-1)" } Block { BlockType Outport Name "Out1" Position [200, 40, 220, 60] IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "In1" SrcPort 1 DstBlock "delay_slr" DstPort 1 } Line { SrcBlock "delay_slr" SrcPort 1 DstBlock "Out1" DstPort 1 } } } Block { BlockType SubSystem Name "mirror_spectrum" Ports [9, 5] Position [755, 32, 845, 248] TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" System { Name "mirror_spectrum" Location [2, 74, 1006, 724] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "sync" Position [80, 93, 110, 107] Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "din0" Position [85, 173, 115, 187] Port "2" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "reo_in0" Position [150, 248, 180, 262] Port "3" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "din1" Position [85, 318, 115, 332] Port "4" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "reo_in1" Position [150, 393, 180, 407] Port "5" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "din2" Position [85, 478, 115, 492] Port "6" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "reo_in2" Position [150, 553, 180, 567] Port "7" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "din3" Position [85, 623, 115, 637] Port "8" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "reo_in3" Position [150, 698, 180, 712] Port "9" IconDisplay "Port number" LatchInput off } Block { BlockType Reference Name "Constant3" Ports [0, 1] Position [240, 136, 280, 154] SourceBlock "xbsIndex_r3/Constant" SourceType "Xilinx Constant Block" const "2^(FFTSize - 1)" equ "P=C" arith_type "Unsigned" n_bits "FFTSize" bin_pt "0" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" iostate "0" explicit_period on period "1" dbl_ovrd off } Block { BlockType Reference Name "Counter" Ports [1, 1] Position [245, 83, 280, 117] SourceBlock "xbsIndex_r3/Counter" SourceType "Xilinx Counter Block" cnt_type "Free Running" n_bits "FFTSize" bin_pt "0" arith_type "Unsigned" start_count "0" cnt_to "Inf" cnt_by_val "1" operation "Up" explicit_period off period "1" load_pin off rst on en off dbl_ovrd off show_param off use_rpm on gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay1" Ports [1, 1] Position [135, 77, 180, 123] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "bram_latency - 2 + 1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay2" Ports [1, 1] Position [390, 27, 435, 73] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "2" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay3" Ports [1, 1] Position [135, 157, 180, 203] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "bram_latency - 1 + 1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay4" Ports [1, 1] Position [135, 302, 180, 348] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "bram_latency - 1 + 1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay5" Ports [1, 1] Position [135, 462, 180, 508] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "bram_latency - 1 + 1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Delay6" Ports [1, 1] Position [135, 607, 180, 653] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "bram_latency - 1 + 1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Mux" Ports [3, 1] Position [415, 155, 430, 205] SourceBlock "xbsIndex_r3/Mux" SourceType "Xilinx Multiplexer Block" inputs "2" precision "Full" arith_type "Signed (2's comp)" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "1" explicit_period off period "1" en off dbl_ovrd off show_param off mux_type off use_rpm off gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Mux1" Ports [3, 1] Position [415, 300, 430, 350] SourceBlock "xbsIndex_r3/Mux" SourceType "Xilinx Multiplexer Block" inputs "2" precision "Full" arith_type "Signed (2's comp)" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "1" explicit_period off period "1" en off dbl_ovrd off show_param off mux_type off use_rpm off gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Mux2" Ports [3, 1] Position [415, 460, 430, 510] SourceBlock "xbsIndex_r3/Mux" SourceType "Xilinx Multiplexer Block" inputs "2" precision "Full" arith_type "Signed (2's comp)" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "1" explicit_period off period "1" en off dbl_ovrd off show_param off mux_type off use_rpm off gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Mux3" Ports [3, 1] Position [415, 605, 430, 655] SourceBlock "xbsIndex_r3/Mux" SourceType "Xilinx Multiplexer Block" inputs "2" precision "Full" arith_type "Signed (2's comp)" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "1" explicit_period off period "1" en off dbl_ovrd off show_param off mux_type off use_rpm off gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Negate" Ports [1, 1] Position [265, 244, 300, 286] SourceBlock "xbsIndex_r3/Negate" SourceType "Xilinx Negate Block" precision "User Defined" arith_type "Unsigned" n_bits "BitWidth" bin_pt "BitWidth - 1" quantization "Truncate" overflow "Wrap" latency "0" explicit_period off period "1" en off dbl_ovrd off use_core on show_param off use_rpm on gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Negate1" Ports [1, 1] Position [265, 389, 300, 431] SourceBlock "xbsIndex_r3/Negate" SourceType "Xilinx Negate Block" precision "User Defined" arith_type "Unsigned" n_bits "BitWidth" bin_pt "BitWidth - 1" quantization "Truncate" overflow "Wrap" latency "0" explicit_period off period "1" en off dbl_ovrd off use_core on show_param off use_rpm on gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Negate2" Ports [1, 1] Position [265, 549, 300, 591] SourceBlock "xbsIndex_r3/Negate" SourceType "Xilinx Negate Block" precision "User Defined" arith_type "Unsigned" n_bits "BitWidth" bin_pt "BitWidth - 1" quantization "Truncate" overflow "Wrap" latency "0" explicit_period off period "1" en off dbl_ovrd off use_core on show_param off use_rpm on gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Negate3" Ports [1, 1] Position [265, 694, 300, 736] SourceBlock "xbsIndex_r3/Negate" SourceType "Xilinx Negate Block" precision "User Defined" arith_type "Unsigned" n_bits "BitWidth" bin_pt "BitWidth - 1" quantization "Truncate" overflow "Wrap" latency "0" explicit_period off period "1" en off dbl_ovrd off use_core on show_param off use_rpm on gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Relational" Ports [2, 1] Position [305, 113, 350, 157] SourceBlock "xbsIndex_r3/Relational" SourceType "Xilinx Relational Block" mode "a>b" latency "1" explicit_period off period "1" en off dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "c_to_ri" Ports [1, 2] Position [205, 234, 245, 276] AttributesFormatString "12_11 r/i" UserDataPersistent on UserData "DataTag3" SourceBlock "casper_library/Misc/c_to_ri" SourceType "c_to_ri" ShowPortLabels on n_bits "BitWidth" bin_pt "BitWidth-1" } Block { BlockType Reference Name "c_to_ri1" Ports [1, 2] Position [205, 379, 245, 421] AttributesFormatString "12_11 r/i" UserDataPersistent on UserData "DataTag4" SourceBlock "casper_library/Misc/c_to_ri" SourceType "c_to_ri" ShowPortLabels on n_bits "BitWidth" bin_pt "BitWidth-1" } Block { BlockType Reference Name "c_to_ri2" Ports [1, 2] Position [205, 539, 245, 581] AttributesFormatString "12_11 r/i" UserDataPersistent on UserData "DataTag5" SourceBlock "casper_library/Misc/c_to_ri" SourceType "c_to_ri" ShowPortLabels on n_bits "BitWidth" bin_pt "BitWidth-1" } Block { BlockType Reference Name "c_to_ri3" Ports [1, 2] Position [205, 684, 245, 726] AttributesFormatString "12_11 r/i" UserDataPersistent on UserData "DataTag6" SourceBlock "casper_library/Misc/c_to_ri" SourceType "c_to_ri" ShowPortLabels on n_bits "BitWidth" bin_pt "BitWidth-1" } Block { BlockType Reference Name "ri_to_c" Ports [2, 1] Position [320, 234, 360, 276] UserDataPersistent on UserData "DataTag7" SourceBlock "casper_library/Misc/ri_to_c" SourceType "ri_to_c" ShowPortLabels on } Block { BlockType Reference Name "ri_to_c1" Ports [2, 1] Position [320, 379, 360, 421] UserDataPersistent on UserData "DataTag8" SourceBlock "casper_library/Misc/ri_to_c" SourceType "ri_to_c" ShowPortLabels on } Block { BlockType Reference Name "ri_to_c2" Ports [2, 1] Position [320, 539, 360, 581] UserDataPersistent on UserData "DataTag9" SourceBlock "casper_library/Misc/ri_to_c" SourceType "ri_to_c" ShowPortLabels on } Block { BlockType Reference Name "ri_to_c3" Ports [2, 1] Position [320, 684, 360, 726] UserDataPersistent on UserData "DataTag10" SourceBlock "casper_library/Misc/ri_to_c" SourceType "ri_to_c" ShowPortLabels on } Block { BlockType Outport Name "sync_out" Position [455, 43, 485, 57] IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "dout0" Position [455, 173, 485, 187] Port "2" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "dout1" Position [455, 318, 485, 332] Port "3" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "dout2" Position [455, 478, 485, 492] Port "4" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "dout3" Position [455, 623, 485, 637] Port "5" IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "din3" SrcPort 1 DstBlock "Delay6" DstPort 1 } Line { SrcBlock "Delay6" SrcPort 1 Points [0, 0] DstBlock "Mux3" DstPort 2 } Line { SrcBlock "Mux3" SrcPort 1 Points [0, 0] DstBlock "dout3" DstPort 1 } Line { SrcBlock "reo_in3" SrcPort 1 DstBlock "c_to_ri3" DstPort 1 } Line { SrcBlock "c_to_ri3" SrcPort 1 DstBlock "ri_to_c3" DstPort 1 } Line { SrcBlock "ri_to_c3" SrcPort 1 Points [15, 0; 0, -60] DstBlock "Mux3" DstPort 3 } Line { SrcBlock "c_to_ri3" SrcPort 2 DstBlock "Negate3" DstPort 1 } Line { SrcBlock "Negate3" SrcPort 1 DstBlock "ri_to_c3" DstPort 2 } Line { SrcBlock "din2" SrcPort 1 DstBlock "Delay5" DstPort 1 } Line { SrcBlock "Delay5" SrcPort 1 Points [0, 0] DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Mux2" SrcPort 1 Points [0, 0] DstBlock "dout2" DstPort 1 } Line { SrcBlock "reo_in2" SrcPort 1 DstBlock "c_to_ri2" DstPort 1 } Line { SrcBlock "c_to_ri2" SrcPort 1 DstBlock "ri_to_c2" DstPort 1 } Line { SrcBlock "ri_to_c2" SrcPort 1 Points [15, 0; 0, -60] DstBlock "Mux2" DstPort 3 } Line { SrcBlock "c_to_ri2" SrcPort 2 DstBlock "Negate2" DstPort 1 } Line { SrcBlock "Negate2" SrcPort 1 DstBlock "ri_to_c2" DstPort 2 } Line { SrcBlock "din1" SrcPort 1 DstBlock "Delay4" DstPort 1 } Line { SrcBlock "Delay4" SrcPort 1 Points [0, 0] DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Mux1" SrcPort 1 Points [0, 0] DstBlock "dout1" DstPort 1 } Line { SrcBlock "reo_in1" SrcPort 1 DstBlock "c_to_ri1" DstPort 1 } Line { SrcBlock "c_to_ri1" SrcPort 1 DstBlock "ri_to_c1" DstPort 1 } Line { SrcBlock "ri_to_c1" SrcPort 1 Points [15, 0; 0, -60] DstBlock "Mux1" DstPort 3 } Line { SrcBlock "c_to_ri1" SrcPort 2 DstBlock "Negate1" DstPort 1 } Line { SrcBlock "Negate1" SrcPort 1 DstBlock "ri_to_c1" DstPort 2 } Line { SrcBlock "sync" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Counter" SrcPort 1 Points [5, 0] DstBlock "Relational" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Relational" DstPort 2 } Line { SrcBlock "Relational" SrcPort 1 Points [40, 0; 0, 30] Branch { Points [0, 145] Branch { Points [0, 160] Branch { DstBlock "Mux2" DstPort 1 } Branch { Points [0, 145] DstBlock "Mux3" DstPort 1 } } Branch { DstBlock "Mux1" DstPort 1 } } Branch { DstBlock "Mux" DstPort 1 } } Line { SrcBlock "din0" SrcPort 1 DstBlock "Delay3" DstPort 1 } Line { SrcBlock "Delay3" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Delay1" SrcPort 1 Points [0, 0; 25, 0] Branch { DstBlock "Counter" DstPort 1 } Branch { Points [0, -50] DstBlock "Delay2" DstPort 1 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "dout0" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 DstBlock "sync_out" DstPort 1 } Line { SrcBlock "reo_in0" SrcPort 1 DstBlock "c_to_ri" DstPort 1 } Line { SrcBlock "c_to_ri" SrcPort 1 DstBlock "ri_to_c" DstPort 1 } Line { SrcBlock "ri_to_c" SrcPort 1 Points [15, 0; 0, -60] DstBlock "Mux" DstPort 3 } Line { SrcBlock "c_to_ri" SrcPort 2 DstBlock "Negate" DstPort 1 } Line { SrcBlock "Negate" SrcPort 1 DstBlock "ri_to_c" DstPort 2 } } } Block { BlockType SubSystem Name "reorder" Ports [3, 3] Position [125, 87, 190, 153] BackgroundColor "[0.501961, 1.000000, 0.501961]" AttributesFormatString "order=2" AncestorBlock "casper_library/Reorder/reorder" UserDataPersistent on UserData "DataTag11" TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" MaskType "reorder" MaskPromptString "Output Order:|Number of inputs|BRAM" " Latency|Map Latency|Double Buffer" MaskStyleString "edit,edit,edit,edit,edit" MaskTunableValueString "on,on,on,on,on" MaskCallbackString "||||" MaskEnableString "on,on,on,on,on" MaskVisibilityString "on,on,on,on,on" MaskToolTipString "on,on,on,on,on" MaskVarAliasString ",,,," MaskVariables "map=@1;n_inputs=@2;bram_latency=@3;" "map_latency=@4;double_buffer=@5;" MaskInitialization "reorder_init(gcb, ...\n 'map', m" "ap, ...\n 'n_inputs', n_inputs, ...\n 'bram_latency', bram_latency, ..." "\n 'map_latency', map_latency, ...\n 'double_buffer', double_buffer);" MaskSelfModifiable on MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskIconUnits "autoscale" MaskValueString "[0 4 2 6 1 5 3 7]|1|2|0|0" MaskTabNameString ",,,," System { Name "reorder" Location [142, 158, 899, 463] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "sync" Position [40, 63, 70, 77] Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "en" Position [25, 118, 55, 132] Port "2" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "din0" Position [495, 83, 525, 97] Port "3" IconDisplay "Port number" LatchInput off } Block { BlockType Reference Name "Counter" Ports [2, 1] Position [95, 56, 145, 109] SourceBlock "xbsIndex_r3/Counter" SourceType "Xilinx Counter Block" cnt_type "Count Limited" n_bits "4" bin_pt "0" arith_type "Unsigned" start_count "0" cnt_to "15" cnt_by_val "1" operation "Up" explicit_period off period "1" load_pin off rst on en on dbl_ovrd off show_param off use_rpm on gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Mux" Ports [3, 1] Position [415, 36, 440, 104] SourceBlock "xbsIndex_r3/Mux" SourceType "Xilinx Multiplexer Block" inputs "2" precision "Full" arith_type "Signed (2's comp)" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "1" explicit_period off period "1" en off dbl_ovrd off show_param off mux_type off use_rpm off gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Slice1" Ports [1, 1] Position [170, 37, 200, 53] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "1" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output off explicit_period off period "1" dbl_ovrd off } Block { BlockType Reference Name "Slice2" Ports [1, 1] Position [170, 77, 200, 93] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Lower Bit Location + Width" nbits "3" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output off explicit_period off period "1" dbl_ovrd off } Block { BlockType Reference Name "bram0" Ports [3, 1] Position [615, 63, 680, 117] SourceBlock "xbsIndex_r3/Single Port RAM" SourceType "Xilinx Single Port Random Access " "Memory" depth "8" initVector "sin(pi*(0:15)/16)" write_mode "Read Before Write" latency "2" init_zero on explicit_period off period "1" rst off init_reg "0" en off dbl_ovrd off show_param off distributed_mem off use_rpm off gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "delay_d0" Ports [1, 1] Position [305, 77, 345, 93] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "0" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "delay_din0" Ports [1, 1] Position [550, 80, 590, 100] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "delay_map1" Ports [1, 1] Position [305, 175, 345, 195] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "0*map_latency" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "delay_sel" Ports [1, 1] Position [305, 37, 345, 53] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "0" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "delay_valid" Ports [1, 1] Position [495, 13, 525, 27] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "3" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "delay_we" Ports [1, 1] Position [305, 115, 345, 135] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "0" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "map1" Ports [1, 1] Position [230, 175, 270, 195] SourceBlock "xbsIndex_r3/ROM" SourceType "Xilinx Single Port Read-Only Memo" "ry" depth "8" initVector "[0 4 2 6 1 5 3 7]" arith_type "Unsigned" n_bits "3" bin_pt "0" latency "0" init_zero on explicit_period off period "1" rst off init_reg "0" en off dbl_ovrd off show_param off distributed_mem on use_rpm off gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "post_sync_delay" Ports [1, 1] Position [135, 159, 155, 201] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "3" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "pre_sync_delay" Ports [1, 1] Position [55, 159, 75, 201] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "0" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "sync_delay_en" Ports [2, 1] Position [85, 159, 125, 201] LinkData { BlockName "Constant" DialogParameters { equ "P=C" } BlockName "Constant1" DialogParameters { equ "P=C" } BlockName "Constant2" DialogParameters { equ "P=C" } BlockName "Constant3" DialogParameters { equ "P=C" } } SourceBlock "casper_library/Delays/sync_delay_" "en" SourceType "sync_delay_en" ShowPortLabels on DelayLen "8" } Block { BlockType Outport Name "sync_out" Position [165, 173, 195, 187] IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "valid" Position [705, 13, 735, 27] Port "2" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "dout0" Position [705, 83, 735, 97] Port "3" IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "sync" SrcPort 1 Points [0, 0] Branch { DstBlock "Counter" DstPort 1 } Branch { DstBlock "pre_sync_delay" DstPort 1 } } Line { SrcBlock "en" SrcPort 1 Points [0, 0] Branch { DstBlock "Counter" DstPort 2 } Branch { DstBlock "sync_delay_en" DstPort 2 } Branch { DstBlock "delay_we" DstPort 1 } } Line { SrcBlock "Counter" SrcPort 1 Points [0, 0] Branch { DstBlock "Slice1" DstPort 1 } Branch { DstBlock "Slice2" DstPort 1 } } Line { SrcBlock "Slice1" SrcPort 1 DstBlock "delay_sel" DstPort 1 } Line { SrcBlock "delay_sel" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "Slice2" SrcPort 1 Points [0, 0] Branch { DstBlock "delay_d0" DstPort 1 } Branch { DstBlock "map1" DstPort 1 } } Line { SrcBlock "delay_d0" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "pre_sync_delay" SrcPort 1 DstBlock "sync_delay_en" DstPort 1 } Line { SrcBlock "sync_delay_en" SrcPort 1 DstBlock "post_sync_delay" DstPort 1 } Line { SrcBlock "post_sync_delay" SrcPort 1 DstBlock "sync_out" DstPort 1 } Line { SrcBlock "delay_we" SrcPort 1 Points [0, 0] Branch { DstBlock "delay_valid" DstPort 1 } Branch { DstBlock "bram0" DstPort 3 } } Line { SrcBlock "delay_valid" SrcPort 1 DstBlock "valid" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "bram0" DstPort 1 } Line { SrcBlock "din0" SrcPort 1 DstBlock "delay_din0" DstPort 1 } Line { SrcBlock "delay_din0" SrcPort 1 DstBlock "bram0" DstPort 2 } Line { SrcBlock "bram0" SrcPort 1 DstBlock "dout0" DstPort 1 } Line { SrcBlock "map1" SrcPort 1 DstBlock "delay_map1" DstPort 1 } Line { SrcBlock "delay_map1" SrcPort 1 DstBlock "Mux" DstPort 3 } } } Block { BlockType SubSystem Name "reorder1" Ports [3, 3] Position [130, 172, 195, 238] BackgroundColor "[0.501961, 1.000000, 0.501961]" AttributesFormatString "order=2" AncestorBlock "casper_library/Reorder/reorder" UserDataPersistent on UserData "DataTag12" TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" MaskType "reorder" MaskPromptString "Output Order:|Number of inputs|BRAM" " Latency|Map Latency|Double Buffer" MaskStyleString "edit,edit,edit,edit,edit" MaskTunableValueString "on,on,on,on,on" MaskCallbackString "||||" MaskEnableString "on,on,on,on,on" MaskVisibilityString "on,on,on,on,on" MaskToolTipString "on,on,on,on,on" MaskVarAliasString ",,,," MaskVariables "map=@1;n_inputs=@2;bram_latency=@3;" "map_latency=@4;double_buffer=@5;" MaskInitialization "reorder_init(gcb, ...\n 'map', m" "ap, ...\n 'n_inputs', n_inputs, ...\n 'bram_latency', bram_latency, ..." "\n 'map_latency', map_latency, ...\n 'double_buffer', double_buffer);" MaskSelfModifiable on MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskIconUnits "autoscale" MaskValueString "[7 3 5 1 6 2 4 0]|1|2|0|0" MaskTabNameString ",,,," System { Name "reorder1" Location [142, 158, 899, 463] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "sync" Position [40, 63, 70, 77] Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "en" Position [25, 118, 55, 132] Port "2" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "din0" Position [495, 83, 525, 97] Port "3" IconDisplay "Port number" LatchInput off } Block { BlockType Reference Name "Counter" Ports [2, 1] Position [95, 56, 145, 109] SourceBlock "xbsIndex_r3/Counter" SourceType "Xilinx Counter Block" cnt_type "Count Limited" n_bits "4" bin_pt "0" arith_type "Unsigned" start_count "0" cnt_to "15" cnt_by_val "1" operation "Up" explicit_period off period "1" load_pin off rst on en on dbl_ovrd off show_param off use_rpm on gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Mux" Ports [3, 1] Position [415, 36, 440, 104] SourceBlock "xbsIndex_r3/Mux" SourceType "Xilinx Multiplexer Block" inputs "2" precision "Full" arith_type "Signed (2's comp)" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "1" explicit_period off period "1" en off dbl_ovrd off show_param off mux_type off use_rpm off gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Slice1" Ports [1, 1] Position [170, 37, 200, 53] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "1" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output off explicit_period off period "1" dbl_ovrd off } Block { BlockType Reference Name "Slice2" Ports [1, 1] Position [170, 77, 200, 93] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Lower Bit Location + Width" nbits "3" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output off explicit_period off period "1" dbl_ovrd off } Block { BlockType Reference Name "bram0" Ports [3, 1] Position [615, 63, 680, 117] SourceBlock "xbsIndex_r3/Single Port RAM" SourceType "Xilinx Single Port Random Access " "Memory" depth "8" initVector "sin(pi*(0:15)/16)" write_mode "Read Before Write" latency "2" init_zero on explicit_period off period "1" rst off init_reg "0" en off dbl_ovrd off show_param off distributed_mem off use_rpm off gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "delay_d0" Ports [1, 1] Position [305, 77, 345, 93] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "0" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "delay_din0" Ports [1, 1] Position [550, 80, 590, 100] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "delay_map1" Ports [1, 1] Position [305, 175, 345, 195] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "0*map_latency" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "delay_sel" Ports [1, 1] Position [305, 37, 345, 53] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "0" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "delay_valid" Ports [1, 1] Position [495, 13, 525, 27] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "3" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "delay_we" Ports [1, 1] Position [305, 115, 345, 135] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "0" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "map1" Ports [1, 1] Position [230, 175, 270, 195] SourceBlock "xbsIndex_r3/ROM" SourceType "Xilinx Single Port Read-Only Memo" "ry" depth "8" initVector "[7 3 5 1 6 2 4 0]" arith_type "Unsigned" n_bits "3" bin_pt "0" latency "0" init_zero on explicit_period off period "1" rst off init_reg "0" en off dbl_ovrd off show_param off distributed_mem on use_rpm off gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "post_sync_delay" Ports [1, 1] Position [135, 159, 155, 201] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "3" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "pre_sync_delay" Ports [1, 1] Position [55, 159, 75, 201] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "0" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "sync_delay_en" Ports [2, 1] Position [85, 159, 125, 201] LinkData { BlockName "Constant" DialogParameters { equ "P=C" } BlockName "Constant1" DialogParameters { equ "P=C" } BlockName "Constant2" DialogParameters { equ "P=C" } BlockName "Constant3" DialogParameters { equ "P=C" } } SourceBlock "casper_library/Delays/sync_delay_" "en" SourceType "sync_delay_en" ShowPortLabels on DelayLen "8" } Block { BlockType Outport Name "sync_out" Position [165, 173, 195, 187] IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "valid" Position [705, 13, 735, 27] Port "2" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "dout0" Position [705, 83, 735, 97] Port "3" IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "sync" SrcPort 1 Points [0, 0] Branch { DstBlock "Counter" DstPort 1 } Branch { DstBlock "pre_sync_delay" DstPort 1 } } Line { SrcBlock "en" SrcPort 1 Points [0, 0] Branch { DstBlock "Counter" DstPort 2 } Branch { DstBlock "sync_delay_en" DstPort 2 } Branch { DstBlock "delay_we" DstPort 1 } } Line { SrcBlock "Counter" SrcPort 1 Points [0, 0] Branch { DstBlock "Slice1" DstPort 1 } Branch { DstBlock "Slice2" DstPort 1 } } Line { SrcBlock "Slice1" SrcPort 1 DstBlock "delay_sel" DstPort 1 } Line { SrcBlock "delay_sel" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "Slice2" SrcPort 1 Points [0, 0] Branch { DstBlock "delay_d0" DstPort 1 } Branch { DstBlock "map1" DstPort 1 } } Line { SrcBlock "delay_d0" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "pre_sync_delay" SrcPort 1 DstBlock "sync_delay_en" DstPort 1 } Line { SrcBlock "sync_delay_en" SrcPort 1 DstBlock "post_sync_delay" DstPort 1 } Line { SrcBlock "post_sync_delay" SrcPort 1 DstBlock "sync_out" DstPort 1 } Line { SrcBlock "delay_we" SrcPort 1 Points [0, 0] Branch { DstBlock "delay_valid" DstPort 1 } Branch { DstBlock "bram0" DstPort 3 } } Line { SrcBlock "delay_valid" SrcPort 1 DstBlock "valid" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "bram0" DstPort 1 } Line { SrcBlock "din0" SrcPort 1 DstBlock "delay_din0" DstPort 1 } Line { SrcBlock "delay_din0" SrcPort 1 DstBlock "bram0" DstPort 2 } Line { SrcBlock "bram0" SrcPort 1 DstBlock "dout0" DstPort 1 } Line { SrcBlock "map1" SrcPort 1 DstBlock "delay_map1" DstPort 1 } Line { SrcBlock "delay_map1" SrcPort 1 DstBlock "Mux" DstPort 3 } } } Block { BlockType SubSystem Name "reorder2" Ports [6, 6] Position [630, 290, 710, 455] BackgroundColor "[0.501961, 1.000000, 0.501961]" AttributesFormatString "order=2" AncestorBlock "casper_library/Reorder/reorder" UserDataPersistent on UserData "DataTag13" TreatAsAtomicUnit off MinAlgLoopOccurrences off RTWSystemCode "Auto" MaskType "reorder" MaskPromptString "Output Order:|Number of inputs|BRAM" " Latency|Map Latency|Double Buffer" MaskStyleString "edit,edit,edit,edit,edit" MaskTunableValueString "on,on,on,on,on" MaskCallbackString "||||" MaskEnableString "on,on,on,on,on" MaskVisibilityString "on,on,on,on,on" MaskToolTipString "on,on,on,on,on" MaskVarAliasString ",,,," MaskVariables "map=@1;n_inputs=@2;bram_latency=@3;" "map_latency=@4;double_buffer=@5;" MaskInitialization "reorder_init(gcb, ...\n 'map', m" "ap, ...\n 'n_inputs', n_inputs, ...\n 'bram_latency', bram_latency, ..." "\n 'map_latency', map_latency, ...\n 'double_buffer', double_buffer);" MaskSelfModifiable on MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskIconUnits "autoscale" MaskValueString "[7 6 5 4 3 2 1 0]|4|2|0|0" MaskTabNameString ",,,," System { Name "reorder2" Location [142, 158, 899, 463] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" ZoomFactor "100" Block { BlockType Inport Name "sync" Position [40, 63, 70, 77] Port "1" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "en" Position [25, 118, 55, 132] Port "2" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "din0" Position [495, 83, 525, 97] Port "3" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "din1" Position [495, 163, 525, 177] Port "4" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "din2" Position [495, 243, 525, 257] Port "5" IconDisplay "Port number" LatchInput off } Block { BlockType Inport Name "din3" Position [495, 323, 525, 337] Port "6" IconDisplay "Port number" LatchInput off } Block { BlockType Reference Name "Counter" Ports [2, 1] Position [95, 56, 145, 109] SourceBlock "xbsIndex_r3/Counter" SourceType "Xilinx Counter Block" cnt_type "Count Limited" n_bits "4" bin_pt "0" arith_type "Unsigned" start_count "0" cnt_to "15" cnt_by_val "1" operation "Up" explicit_period off period "1" load_pin off rst on en on dbl_ovrd off show_param off use_rpm on gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Mux" Ports [3, 1] Position [415, 36, 440, 104] SourceBlock "xbsIndex_r3/Mux" SourceType "Xilinx Multiplexer Block" inputs "2" precision "Full" arith_type "Signed (2's comp)" n_bits "8" bin_pt "2" quantization "Truncate" overflow "Wrap" latency "1" explicit_period off period "1" en off dbl_ovrd off show_param off mux_type off use_rpm off gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "Slice1" Ports [1, 1] Position [170, 37, 200, 53] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Upper Bit Location + Width" nbits "1" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output off explicit_period off period "1" dbl_ovrd off } Block { BlockType Reference Name "Slice2" Ports [1, 1] Position [170, 77, 200, 93] SourceBlock "xbsIndex_r3/Slice" SourceType "Xilinx Slice Block" mode "Lower Bit Location + Width" nbits "3" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" boolean_output off explicit_period off period "1" dbl_ovrd off } Block { BlockType Reference Name "bram0" Ports [3, 1] Position [615, 63, 680, 117] SourceBlock "xbsIndex_r3/Single Port RAM" SourceType "Xilinx Single Port Random Access " "Memory" depth "8" initVector "sin(pi*(0:15)/16)" write_mode "Read Before Write" latency "2" init_zero on explicit_period off period "1" rst off init_reg "0" en off dbl_ovrd off show_param off distributed_mem off use_rpm off gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "bram1" Ports [3, 1] Position [615, 143, 680, 197] SourceBlock "xbsIndex_r3/Single Port RAM" SourceType "Xilinx Single Port Random Access " "Memory" depth "8" initVector "sin(pi*(0:15)/16)" write_mode "Read Before Write" latency "2" init_zero on explicit_period off period "1" rst off init_reg "0" en off dbl_ovrd off show_param off distributed_mem off use_rpm off gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "bram2" Ports [3, 1] Position [615, 223, 680, 277] SourceBlock "xbsIndex_r3/Single Port RAM" SourceType "Xilinx Single Port Random Access " "Memory" depth "8" initVector "sin(pi*(0:15)/16)" write_mode "Read Before Write" latency "2" init_zero on explicit_period off period "1" rst off init_reg "0" en off dbl_ovrd off show_param off distributed_mem off use_rpm off gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "bram3" Ports [3, 1] Position [615, 303, 680, 357] SourceBlock "xbsIndex_r3/Single Port RAM" SourceType "Xilinx Single Port Random Access " "Memory" depth "8" initVector "sin(pi*(0:15)/16)" write_mode "Read Before Write" latency "2" init_zero on explicit_period off period "1" rst off init_reg "0" en off dbl_ovrd off show_param off distributed_mem off use_rpm off gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "delay_d0" Ports [1, 1] Position [305, 77, 345, 93] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "0" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "delay_din0" Ports [1, 1] Position [550, 80, 590, 100] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "delay_din1" Ports [1, 1] Position [550, 160, 590, 180] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "delay_din2" Ports [1, 1] Position [550, 240, 590, 260] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "delay_din3" Ports [1, 1] Position [550, 320, 590, 340] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "1" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "delay_map1" Ports [1, 1] Position [305, 175, 345, 195] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "0*map_latency" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "delay_sel" Ports [1, 1] Position [305, 37, 345, 53] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "0" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "delay_valid" Ports [1, 1] Position [495, 13, 525, 27] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "3" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "delay_we" Ports [1, 1] Position [305, 115, 345, 135] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "0" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "map1" Ports [1, 1] Position [230, 175, 270, 195] SourceBlock "xbsIndex_r3/ROM" SourceType "Xilinx Single Port Read-Only Memo" "ry" depth "8" initVector "[7 6 5 4 3 2 1 0]" arith_type "Unsigned" n_bits "3" bin_pt "0" latency "0" init_zero on explicit_period off period "1" rst off init_reg "0" en off dbl_ovrd off show_param off distributed_mem on use_rpm off gen_core off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "post_sync_delay" Ports [1, 1] Position [135, 159, 155, 201] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "3" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "pre_sync_delay" Ports [1, 1] Position [55, 159, 75, 201] SourceBlock "xbsIndex_r3/Delay" SourceType "Xilinx Delay Block" latency "0" reg_retiming off explicit_period off period "1" en off accept_only_valid off init_zero on dbl_ovrd off show_param off xl_area "[0, 0, 0, 0, 0, 0, 0]" xl_use_area off } Block { BlockType Reference Name "sync_delay_en" Ports [2, 1] Position [85, 159, 125, 201] LinkData { BlockName "Constant" DialogParameters { equ "P=C" } BlockName "Constant1" DialogParameters { equ "P=C" } BlockName "Constant2" DialogParameters { equ "P=C" } BlockName "Constant3" DialogParameters { equ "P=C" } } SourceBlock "casper_library/Delays/sync_delay_" "en" SourceType "sync_delay_en" ShowPortLabels on DelayLen "8" } Block { BlockType Outport Name "sync_out" Position [165, 173, 195, 187] IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "valid" Position [705, 13, 735, 27] Port "2" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "dout0" Position [705, 83, 735, 97] Port "3" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "dout1" Position [705, 163, 735, 177] Port "4" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "dout2" Position [705, 243, 735, 257] Port "5" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "dout3" Position [705, 323, 735, 337] Port "6" IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "sync" SrcPort 1 Points [0, 0] Branch { DstBlock "Counter" DstPort 1 } Branch { DstBlock "pre_sync_delay" DstPort 1 } } Line { SrcBlock "en" SrcPort 1 Points [0, 0] Branch { DstBlock "Counter" DstPort 2 } Branch { DstBlock "sync_delay_en" DstPort 2 } Branch { DstBlock "delay_we" DstPort 1 } } Line { SrcBlock "Counter" SrcPort 1 Points [0, 0] Branch { DstBlock "Slice1" DstPort 1 } Branch { DstBlock "Slice2" DstPort 1 } } Line { SrcBlock "Slice1" SrcPort 1 DstBlock "delay_sel" DstPort 1 } Line { SrcBlock "delay_sel" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "Slice2" SrcPort 1 Points [0, 0] Branch { DstBlock "delay_d0" DstPort 1 } Branch { DstBlock "map1" DstPort 1 } } Line { SrcBlock "delay_d0" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "pre_sync_delay" SrcPort 1 DstBlock "sync_delay_en" DstPort 1 } Line { SrcBlock "sync_delay_en" SrcPort 1 DstBlock "post_sync_delay" DstPort 1 } Line { SrcBlock "post_sync_delay" SrcPort 1 DstBlock "sync_out"